In recent years, with the increase in transmission capacity, an optical communication using, for example, optical fibers has been developed dramatically in the field of communication. In the optical communication, an information processing apparatus such as an optical module that converts an electric signal into an optical signal is used, and data transmission and reception by optical signals are performed between information processing apparatuses of a transmitting side and a receiving side via a transmission path such as an optical fiber.
In order to reliably transmit and receive a digital signal in the optical communication, the information processing apparatus of the receiving side is required to determine each data bit at a correct timing. The information processing apparatus of the receiving side determines data by using timing information for determining the timing of reading the data. As a means for acquiring the timing information, there is a method in which the information processing apparatus of the transmitting side transmits a clock signal in parallel to a data signal. In such a method, the information processing apparatus of the receiving side reads the data, for example, at a vertical rising timing of the received clock signal.
In this regard, considering that it is difficult to adjust the timing of the clock transmitted in parallel to the data due to a transmission delay in a high-speed data communication such as the optical communication, a method has been frequently adopted recently which embeds clock information in the data signal and recovers the clock by the information processing apparatus of the receiving side. The recovery of the clock is performed by a signal recovery (clock data recovery (CDR)) circuit of the information processing apparatus of the receiving side.
As for the signal recovery circuit, a phase locked loop (PLL) circuit is used, which includes, for example, a phase/frequency comparator, a loop filter, and a voltage controlled oscillator (VCO). The signal recovery circuit recovers a clock signal by adjusting the control voltage for the VCO for the clock by comparing with the phase of an internal reference clock signal with a data edge corresponding to the falling or vertical rising of the received data signal by using, for example, the PLL circuit.
Here, as for a recovery technique of the clock signal, there is related art that suppresses the phase shift by masking a phase detection when the same sign is continuously detected. Further, there is related art that widens a synchronization pull-in range of the phase locked loop by using a frequency detector. In addition, there is related art that integrates a predetermined number of clocks and adjusts the control voltage for each cycle of the integrated unit group. Further, there is related art that maintains the output frequency set before the supply of a reference clock signal is interrupted at the time of interrupting the supply of the reference clock signal.
Related techniques are disclosed in, for example, Japanese Laid-open Patent Publication Nos. 2017-073700, 10-285150, and 2013-017076, and Japanese Laid-open Utility Model Publication No. 05-068132.